My Experience

HELLO AGAIN! This is where you can explore my professional and technical background. Below you will find my work and research experience spanning power electronics, analog design, and beyond. If any of it sparks your interest or if you're an expert in these areas please reach out :)

Work Experience

University of Central Florida | Undergraduate Research Assistant

Orlando, FL | February 2026 – Present

  • Designed a 20-stage Cockcroft-Walton voltage multiplier PCB in Altium for integration into a medium-voltage power module

  • Optimized MOV placement in an MV hybrid DC circuit breaker power stack using PINN, improving current balance by 48%

  • Performed aluminum wire bonding on MOSFET and PCB interconnects using a TPT HB75 to improve thermal dissipation

  • Simulated voltage multiplier circuits in Simulink to determine ideal frequencies, voltage, capacitor ratings, and diode values

Arup Group | Electrical Engineering Intern

San Francisco, CA | May 2025 – August 2025

  • Designed fiber optic wiring systems for Equinix’s new 280,000 sqft SV18 & SV19 data center, supporting 34 MW of power

  • Conducted site visits at UCSF Parnassus Hospital, installing 4.8–27 kV switchgear and electrical wiring per NEC standards

  • Validated electrical designs across 12 major projects in coordination with 30+ contractors using UniFi and SKM Power Tools

  • Engineered power distribution systems in Revit MEP for industrial buildings up to 850,000 sqft, focusing on system reliability

Lockheed Martin Corporation | Analog Design Engineering Intern

Orlando, FL | August 2024 – May 2025

  • Performed deep Monte Carlo simulations on PUFs, generating 10+ million data points to evaluate randomness for security

  • Evaluated 200+ IC designs in Synopsys, analyzing power, performance, area, and functionality across multiple circuit designs

  • Simulated 25 AC/DC and RLC circuits weekly in LTspice, improving efficiency by minimizing conduction and switching losses

  • Created 10-15 block diagrams from full EDA schematics in Visio to communicate system architecture to cross-functional teams

University of Central Florida | Undergraduate Learning Assistant

Orlando, FL | January 2025 – May 2025

  • Led 2 weekly office-hour sessions supporting 120+ students in digital systems topics including Boolean algebra and logic gates

  • Developed 150+ problems with 4 fellow ULAs throughout the semester, raising average scores by 10% from Midterm 1 to 2

  • Designed synchronous and asynchronous sequential logic examples to connect classroom concepts with real-world applications

  • Supported graduate TAs in weekly lab sessions debugging Verilog code for BASYS-3 FPGA boards and proofreading lab reports

Research Work

Undergraduate Research: Harmonic Distortion in Wide-Bandgap Power Conversion

April 2026 - Present

  • Simulated a single-phase GaN H-bridge inverter in LTspice with 20 kHz SPWM, achieving 19.2 V peak output at 0.03% THD-F

  • Built and validated an FFT-based THD-F pipeline in MATLAB with harmonic detection to the 50th order, confirmed to <0.01% error

  • Diagnosed high-side gate drive failure in LTspice H-bridge by replacing NMOS with ideal switch models, restoring correct SPWM output

Independent Research Study: GaN-Based High-Frequency DC-DC Converter

January 2026 - Present

  • Designed a 15W GaN synchronous buck converter from first principles, deriving component values for 2MHz operation

  • Simulated GaN buck converter in LTspice using EPC2020 SPICE models, characterizing efficiency across load and frequency

  • Developed MATLAB loss model separating switching, conduction, and gate drive losses across a 1–10MHz frequency sweep

  • Laid out GaN converter PCB in Altium applying high-frequency layout techniques including minimized switching loop area

Research Paper: The Global Data Center Dilemma - Under Review

January 2026 - Present

  • Compared generation mix and grid carbon intensity (g CO2/kWh), analyzing coal, natural gas, hydro, wind, and solar sources

  • Analyzed grid interconnection constraints, comparing queue sizes (<5 GW to 400+ GW) and wait times (1–2 to 5–10+ years)

  • Evaluated data center environmental impacts including carbon emissions, thermal discharge, and infrastructure sustainability